This application claims priority to prior Japanese patent application JP 2005-316463, the disclosure of which is incorporated herein by reference.
This invention relates to a semiconductor memory device and, in particular, to a shared sense amplifier circuit or portion.
In recent years, a semiconductor memory device is more and more improved towards a larger capacity and higher integration. In a dynamic random access memory (hereinafter will be abbreviated to a DRAM), products having a memory capacity of 1 Gbit are developed. By increasing the memory capacity, the semiconductor memory device is miniaturized. In order to increase the memory capacity, various proposals have been made.
In the DRAM having a large capacity, a shared sense amplifier portion is used. The sense amplifier portion is supplied with data selectively from memory cells on opposite sides of the sense amplifier portion and carries out a sensing operation. Further, word lines for controlling the memory cells are not directly inputted from a row decoder to the memory cells but a divisional decoding system is used. Following an increase in operation speed of the semiconductor memory device, use is made of a clocking method of temporarily disconnecting a memory cell portion and a sense amplifier portion upon sensing in order to increase a sensing speed. In this method, clocking is performed by providing a transfer gate for disconnecting the memory cell portion and the sense amplifier portion. A whole capacity of a bit line pair (D/DB) is not charged and discharged but a part in the sense amplifier portion alone is amplified at a high speed.
As a countermeasure against a noise between bit lines, the bit lines are twisted inside a memory cell array to reduce a coupling noise between adjacent bit lines and to avoid an operation error due to the noise. Thus, the shared sense amplifier portion, the clocking method using the transfer gate, and the noise countermeasure have been proposed and put into practical use. In the present status, however, following the increase in scale and the miniaturization, several problems arise around the sense amplifier portion for supplying and receiving data to and from the memory cells.
Referring to FIGS. 1 to 4, those problems in the present status will be described. Referring to FIG. 1, an existing sense amplifier portion SA is connected to left and right transfer gates TG-L/R and left and right memory cell arrays MA-L/R via bit line pairs D/DB. The sense amplifier portion SA is of a shared type. Memory cells are arranged at intersecting points of bit lines and word lines. For example, description will be made of an operation in case where one of the word lines of the left memory cell array MA-L is selected. The left transfer gate TG-L is activated and a potential difference is produced in the bit line pair D/DB. The word lines of the right memory cell array MA-R and the transfer gate TG-R are inactivated. The bit line pairs D/DB of the right memory cell array MA-R are disconnected from the sense amplifier portion SA.
The sense amplifier portion SA can perform signal amplification once the potential difference in the bit line pair D/DB is obtained. Therefore, when the potential difference in the bit line pair D/DB is obtained in the sense amplifier portion, the left memory cell array MA-L is disconnected again by the left transfer gate TG-L. By amplifying a part in the sense amplifier portion SA alone in the above-mentioned manner, a sensing speed can be increased. Data amplified by the sense amplifier portion SA and read out pass through a main amplifier to be outputted from an input/output circuit. Simultaneously, the left transfer gate TG-L is activated again and rewriting into the memory cells is carried out. When the data reading operation and the rewriting operation into the memory cells are completed, the left transfer gate TG-L is disconnected. Then, a next cycle is started.
In the shared sense amplifier portion, the memory cells MA-L/R and the sense amplifier portion SA are disconnected by the transfer gates TG-L/R. In order to increase the sensing speed, a whole capacity of the bit line pair D/DB is not charged or discharged upon sensing. Instead, use is made of the clocking method of temporarily disconnecting the memory cell arrays MA-L/R and the sense amplifier portion SA and amplifying a part in the sense amplifier portion SA alone. After amplification by the sense amplifier portion SA, the memory cell arrays MA-L/R and the sense amplifier portion SA are connected again by the transfer gates TG. Thus, by the use of the transfer gates TG, clocking is performed to switch connection/disconnection/connection. In this manner, the reading operation can be carried out at a high speed.
Referring to FIG. 2, two sets of the sense amplifiers and the transfer gates are adjacent to each other. The bit lines from the memory cells are connected to the sense amplifier portion SA via the transfer gates TG-L/R. Two sets of the bit lines D/DB in the sense amplifiers are depicted by A/B and D/E as illustrated in the figure. In case of a CMOS circuit, each of the sense amplifiers comprises two CMOS inverter circuits each of which is loop-connected. The CMOS inverter circuit comprises a PMOS region provided with a load MOS transistor and a NMOS region provided with a driver MOS transistor. As power supplies, a high power supply voltage SAP and a low power supply voltage SAN are applied. Each sense amplifier of the sense amplifier portion SA amplifies data from a selected memory cell.
Referring to FIG. 3, the layout around the sense amplifiers in FIG. 2 will be described. Herein, only two sets of the bit line pairs A/B and D/E are shown. By repeating this layout, an array is formed. In FIG. 3, each of the PMOS transistor and the NMOS transistor forming the sense amplifier is implemented by a straight channel. For example, in the NMOS region, the transistors on the left side use the bit lines A and E as drains, C as a source, and the bit lines B and D as gates. The bit lines A and E are connected to the drains by bit contacts. The source C is shared. The gates are connected to the bit lines B and D by gate poly contacts. The transistors on the right side use the bit lines B and D as drains, C as a source, and the bit lines A and E as gates. The source C is shared with the adjacent sense amplifier.
Referring to FIG. 4, description will be made of the layout of a second existing sense amplifier portion. In FIG. 4, transistors of the sense amplifier are implemented by a ring-shaped channel. The channel in a ring shape avoids the Kink effect and, therefore, effectively reduces an unbalance. The transistors on the left side in the figure use the bit lines A and D as drains, C as a source, and the bit lines B and E as gates. The transistors on the right side use the bit lines B and E as drains, C as a source, and the bit lines A and D) as gates. The source C is shared. The layout is applicable to both of the drive-side NMOS transistor and the load-side PMOS transistor of the sense amplifier.
As an operation of the above-mentioned sense amplifier portion, clocking is performed by the use of the transfer gates TG so that the capacity of the bit line connected to the sense amplifier upon activation is relatively small. This is suitable for a high-speed operation. However, as illustrated in FIGS. 3 and 4, the bit lines B and D are adjacent to each other throughout a whole area in the sense amplifier portion. Therefore, the sensing speed is decreased by a noise from the adjacent bit line. In the worst case, judgment error is caused to occur.
In the semiconductor memory device in which clocking is performed by the use of the transfer gate TG, an adjacent coupling noise in the sense amplifier portion is not negligible although it was negligible in the past. In the existing sense amplifier portion, specific bit lines are adjacent to each other throughout the whole area in the sense amplifier portion so that the sensing speed is decreased in response to a noise from the adjacent bit line and, in the worst case, judgment error is caused to occur. The reason why the first problem arises is that miniaturization advances in recent years and the influence of the adjacent coupling noise in the sense amplifier portion is increased.
The countermeasure against a noise between the bit lines and the reduction in area of the sense amplifier are disclosed in the following patent documents. In Japanese Unexamined Patent Application Publication (JP-A) No. S63-148489, intersecting points are provided inside a memory cell array and bit lines are twisted at the intersecting points. By twisting the bit lines, a coupling noise between the adjacent bit lines is suppressed and an operation error due to the noise is avoided. However, the intersecting points are required to twist the bit lines so that the layout area is increased. In Japanese Unexamined Patent Application Publication (JP-A) No. 2000-123574, bit lines of a sense amplifier and a main bit line are made to intersect each other at connection points (selector switches YSW) between the bit lines of the sense amplifier and the main bit line. In Japanese Unexamined Patent Application Publication (JP-A) No. H2-166690, a diffusion layer of the sense amplifier is shared so as to reduce an area. However, any of the above-mentioned patent documents does not raise a problem about generation of a noise between wirings in the sense amplifier and does not describe the countermeasure against the problem.
As described above, the above-mentioned patent documents are addressed to the countermeasure against a noise between the bit lines disposed on the memory cell array and do not describe a countermeasure against the problem of generation of a noise between wirings in the sense amplifier portion because of unawareness of the problem. However, following the advancement of miniaturization and use of the clocking method, the bit lines in the sense amplifier portion are closely adjacent to one another. As a consequence, the influence of the adjacent coupling noise is increased to become unnegligible. However, as compared with the capacity of a whole of the bit lines, the influence is small. Therefore, in the layout of the existing sense amplifier portion, no consideration is made about twisting the bit lines in the sense amplifier portion.
The reason is as follows. In case where the bit lines are twisted in the sense amplifier portion, another wiring layer must be used via a contact so that the layout area is increased. In the conventional technique, there is no idea about twisting the bit lines in the sense amplifier portion, which is accompanied with an increase in layout area. Therefore, the problem about generation of a noise between wirings inside the sense amplifier portion is left unsolved.